// Copyright (C) 2021  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.

// PROGRAM		"Quartus Prime"
// VERSION		"Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition"
// CREATED		"Thu Aug 18 15:34:31 2022"

module N_bit_adder(input1,input2,answer);
parameter N=8;
input [N-1:0] input1,input2;
   output [N-1:0] answer;
   wire  carry_out;
   wire [N-1:0] carry;
   genvar i;
   generate 
   for(i=0;i<N;i=i+1)
     begin: generate_N_bit_Adder
   		if(i==0) 
  			HA f(input1[0],input2[0],answer[0],carry[0]);
   		else
  			FA f(input1[i],input2[i],carry[i-1],answer[i],carry[i]);
     	end
   assign carry_out = carry[N-1];
   endgenerate
endmodule 
          
module Four_bit_adder(input1,input2,answer);
input [3:0] input1,input2;
   output [3:0] answer;
   wire  carry_out;
   wire [3:0] carry;
  	HA f0(input1[0],input2[0],answer[0],carry[0]);
   	FA f1(input1[1],input2[1],carry[0],answer[1],carry[1]);    
   	FA f2(input1[2],input2[2],carry[1],answer[2],carry[2]);   
   	FA f3(input1[3],input2[3],carry[2],answer[3],carry[3]);
   assign carry_out = carry[3];
endmodule           
          

module HA ( input a, input b, output s, output c );  
    assign  s = a ^ b; 
	assign  c = a & b;  	  
endmodule  

module FA ( input a, input b, input c_in, output s, output c_out );     
    wire somma_par;
    wire carry1,carry2;
 
	HA  HA1(a,b,somma_par,carry1); 
	HA  HA2(c_in,somma_par,s,carry2);  
	
	assign c_out = carry1 | carry2;
endmodule