module my_echo_decoder_v1(
clk         , // Clock Input
address     , // Address Input
readdata        , // Data output
writedata        , // Data input
chipselect          , // Chip Select
write          , // Write Enable/Read Enable
read   ,
reset_n		,		// Reset
trig,
echo
);

parameter DATA_WIDTH = 32 ;
parameter ADDR_WIDTH = 4 ;
parameter SUBSAMP = 2 ;


//--------------Input/Output Ports----------------------- 
input                  clk         ;
input [ADDR_WIDTH-1:0] address     ;
input                  chipselect          ;
input                  write          ;
input read  ;
input                  reset_n          ; 
input [DATA_WIDTH-1:0]  writedata       ;
output reg				   trig;
input							echo;
output reg [DATA_WIDTH-1:0]  readdata       ;

reg echo_del,echo_reg;
reg [SUBSAMP-1:0] count;
reg [DATA_WIDTH-1:0] count_pulse;
reg [7:0] count_mill;

always @(posedge clk) count=count+1;
always @(posedge clk) if (count==0) echo_reg <= echo; 
always @(posedge clk) if (count==0) echo_del <= echo_reg; 



always @(posedge clk or negedge reset_n)
begin
 if (reset_n==0)
   begin
      trig<=0;
		count_mill<=0;
	end	
  else if (count==0)
  begin
	  if (count_mill < 100) count_mill<=count_mill+1; else count_mill<=0;
	  if (count_mill<12) trig<=1; else trig <=0;
  end
 end
  
 

always @(posedge clk or negedge reset_n)
begin
 if (reset_n==0)
      count_pulse<=0;
 else if ((echo_del==0)&&(echo_reg==1))
       count_pulse<=0;
 else if (echo_reg==1)
       count_pulse=count_pulse+1;
end
		 

 
always @ (posedge clk or negedge reset_n)
begin
   if (reset_n==0 ) readdata <= 0;
   else if((echo_del==1)&&(echo_reg==0))
		readdata <= count_pulse;
end
		
		
		
endmodule