module my_simpleI2C_rw_v2 (clk, address, readdata, writedata, read, write, reset_n,sda,scl);

parameter ADDRSIZE = 2;
parameter WORDSIZE = 32;
parameter FREQDIV =2;

input clk;
input [ADDRSIZE-1:0] address;
output reg [WORDSIZE-1:0] readdata;
input [WORDSIZE-1:0] writedata;
input read,write;
input reset_n;
inout sda,scl;

reg [WORDSIZE-1:0] Mem [0:(1<<ADDRSIZE)-1];
reg [WORDSIZE-1:0] out_bits;
reg [FREQDIV-1:0] count;

// assign readdata = (read) ? Mem[address] : {WORDSIZE{1'b0}};

assign sda = (sda_o) ? 1'bz: sda_o;
assign scl = (scl_o) ? 1'bz: scl_o;
 
//assign sda = sda_o;
//assign scl = scl_o;

reg [8:0] counter_reg;
reg [3:0] cmd_sda;
reg [3:0] cmd_scl;
reg sda_i,sda_o,scl_o;

wire [1:0] counter_4=counter_reg[1:0];
wire [6:0] counter_bit=counter_reg[8:2];
wire [31:0] settings,tmp_mem;
wire [28:0] bits_to_write,ctrl_to_write;
wire [38:0] bits_to_read,ctrl_to_read;

wire w_nr;
reg ack1,ack2,ack3;

assign tmp_mem=Mem[0];
assign settings=Mem[3];
assign w_nr=settings[0];

assign bits_to_write={1'b0,tmp_mem[23:17],1'b0,1'b1,tmp_mem[15:8],1'b1,tmp_mem[7:0],1'b1,1'b1};
assign ctrl_to_write={1'b1,27'b0,1'b1};
assign bits_to_read={1'b0,tmp_mem[23:17],1'b0,1'b1,tmp_mem[15:8],1'b1,1'b0,tmp_mem[23:17],12'hfff};
assign ctrl_to_read={1'b1,18'b0,1'b1,18'b0,1'b1};


always @(posedge clk)
  begin
  if (write && address==0) Mem[0] = writedata;
  if (write && address==3) Mem[3] = writedata;
  end
  
always @(posedge clk)
  if (read) readdata= Mem[address];
  
always @(posedge clk)
    count=count+1;
	 

always @(posedge clk) 
begin
if (address==3 && write)  counter_reg=8'd160;
else if ((counter_reg <= 8'd160) && (count==0))
begin
 counter_reg=counter_reg-1;    
if (counter_bit==0) begin cmd_sda=4'b1111; cmd_scl=4'b1111; end
else if ((counter_bit>39)) begin cmd_sda=4'b1111; cmd_scl=4'b1111; end
else if ((counter_bit>29)&&(w_nr)) begin cmd_sda=4'b1111; cmd_scl=4'b1111; end
else if (w_nr) 
  begin
	 case ({bits_to_write[counter_bit-1],ctrl_to_write[counter_bit-1]})
		2'b01: begin cmd_sda=4'b1000; cmd_scl=4'b1110; end
		2'b11: begin cmd_sda=4'b0001; cmd_scl=4'b0111; end
		2'b00: begin cmd_sda=4'b0000; cmd_scl=4'b0110; end
		2'b10: begin cmd_sda=4'b1111; cmd_scl=4'b0110; end
		default: begin cmd_sda=4'b1111; cmd_scl=4'b1111; end
	endcase
	end
else
   case ({bits_to_read[counter_bit-1],ctrl_to_read[counter_bit-1]})
		2'b01: begin cmd_sda=4'b1000; cmd_scl=4'b1110; end
		2'b11: begin cmd_sda=4'b0001; cmd_scl=4'b0111; end
		2'b00: begin cmd_sda=4'b0000; cmd_scl=4'b0110; end
		2'b10: begin cmd_sda=4'b1111; cmd_scl=4'b0110; end
		default: begin cmd_sda=4'b1111; cmd_scl=4'b1111; end
	endcase	
  sda_o=cmd_sda[counter_4];
  scl_o=cmd_scl[counter_4];
end
end


always @(posedge clk) 
	begin
	  if (counter_reg==80) ack1=sda;
	  if (counter_reg==44) ack2=sda;
	  if (w_nr) 
	     begin if (counter_reg==8) ack3=sda; end
	  else
	   begin
			if (counter_reg==12) ack3=sda;
			if ((counter_4==3) && (counter_bit>=3)&&(counter_bit<=10)) out_bits[counter_bit-3]<=sda; 
		end

	end
	 
	
	
always @(posedge clk)
  if (counter_reg==8'b0)
   begin
   Mem[1] = out_bits;
	Mem[2] = {29'h0,ack1,ack2,ack3};
	end

endmodule