module SimpleRAM (clk, address, readdata, writedata, read, write, reset_n);

parameter ADDRSIZE = 1;
parameter WORDSIZE = 32;

input clk;
input [ADDRSIZE-1:0] address;
output [WORDSIZE-1:0] readdata;
input [WORDSIZE-1:0] writedata;
input read,write;
input reset_n;

reg [WORDSIZE-1:0] Mem [0:(1<<ADDRSIZE)-1];

assign readdata = (read) ? Mem[address] : {WORDSIZE{1'bz}};

always @(posedge clk)
  if (write)
    Mem[address] = writedata;

endmodule