module simple_rom(
               // inputs:
                address,
                clock,
                reset_n,

               // outputs:
                readdata
             );

  output  [31:0] readdata;
  input   [2:0]    address;
  input            clock;
  input            reset_n;

  reg    [31:0] readdata;
  reg    [2:0]  addr_reg;

always @( posedge clock)
	addr_reg=address;

always @ (addr_reg)
	case (addr_reg)
		3'h0: readdata = 32'h0001;
		3'h1: readdata = 32'h0002;
		3'h2: readdata = 32'h0003;
		3'h3: readdata = 32'h0004;
		3'h4: readdata = 32'h0011;
		3'h5: readdata = 32'h0012;
		3'h6: readdata = 32'h0013;
		3'h7: readdata = 32'h0014;
	endcase
endmodule