// Copyright (C) 2022  Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions 
// and other software and tools, and any partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License 
// Subscription Agreement, the Intel Quartus Prime License Agreement,
// the Intel FPGA IP License Agreement, or other applicable license
// agreement, including, without limitation, that your use is for
// the sole purpose of programming logic devices manufactured by
// Intel and sold by Intel or its authorized distributors.  Please
// refer to the applicable agreement for further details, at
// https://fpgasoftware.intel.com/eula.

// PROGRAM		"Quartus Prime"
// VERSION		"Version 22.1std.0 Build 915 10/25/2022 SC Lite Edition"
// CREATED		"Tue Jul 25 09:49:59 2023"

module Counter6digit_sync(
	clk,
	res,
	DIG0,
	DIG1,
	DIG2,
	DIG3,
	DIG4,
	DIG5
);


input wire	clk;
input wire	res;
output wire	[3:0] DIG0;
output wire	[3:0] DIG1;
output wire	[3:0] DIG2;
output wire	[3:0] DIG3;
output wire	[3:0] DIG4;
output wire	[3:0] DIG5;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;
wire	SYNTHESIZED_WIRE_4;
wire	SYNTHESIZED_WIRE_5;



assign	SYNTHESIZED_WIRE_0 = 1;


Modular_counter_sync	b2v_inst0(
	.clk(clk),
	.enable(SYNTHESIZED_WIRE_0),
	.reset(res),
	.carry(SYNTHESIZED_WIRE_1),
	.count(DIG0));
	defparam	b2v_inst0.MODULE = 9;


Modular_counter_sync	b2v_inst1(
	.clk(clk),
	.enable(SYNTHESIZED_WIRE_1),
	.reset(res),
	.carry(SYNTHESIZED_WIRE_2),
	.count(DIG1));
	defparam	b2v_inst1.MODULE = 9;

Modular_counter_sync	b2v_inst2(
	.clk(clk),
	.enable(SYNTHESIZED_WIRE_2),
	.reset(res),
	.carry(SYNTHESIZED_WIRE_3),
	.count(DIG2));
	defparam	b2v_inst2.MODULE = 9;


Modular_counter_sync	b2v_inst3(
	.clk(clk),
	.enable(SYNTHESIZED_WIRE_3),
	.reset(res),
	.carry(SYNTHESIZED_WIRE_4),
	.count(DIG3));
	defparam	b2v_inst3.MODULE = 9;


Modular_counter_sync	b2v_inst4(
	.clk(clk),
	.enable(SYNTHESIZED_WIRE_4),
	.reset(res),
	.carry(SYNTHESIZED_WIRE_5),
	.count(DIG4));
	defparam	b2v_inst4.MODULE = 9;


Modular_counter_sync	b2v_inst5(
	.clk(clk),
	.enable(SYNTHESIZED_WIRE_5),
	.reset(res),
	
	.count(DIG5));
	defparam	b2v_inst5.MODULE = 9;
	
	



endmodule