module clock_divider (
  input clk_in,
  input [7:0] time_tot,time_high,
  output clk_out
);

  reg [7:0] counter;
  reg clk;

  always @(posedge clk_in) 
  begin
    counter <= counter + 1;
    if (counter < time_high)  clk <= 1;
    else if (counter < time_tot) clk <=0;
	 else counter<=0;
  end

  assign clk_out = clk;
  
 endmodule