module edge_detector (
  input clk,signal,
  output edgeH,edgeL
);

  reg previous_signal, twocycle_signal;
  
   always @(posedge clk) 
	 begin 
	  previous_signal <= signal;
	  twocycle_signal <= previous_signal;
	 end
	 
	
   assign edgeH = ~twocycle_signal & previous_signal;   
	assign edgeL = twocycle_signal & ~previous_signal;
	
endmodule