module TOP_SPI (i_clk,i_res_L,o_SPI_Clk,o_SPI_Data,o_CS_L );
  input i_clk,i_res_L;
  output o_SPI_Clk,o_SPI_Data;
  output reg o_CS_L;
  
  wire w_data_rdy;
  wire [15:0] w_data;
  wire w_data_req;
  
  SPI_Lut DataGEN(.i_clk(i_clk),.i_res_L(i_res_L),
                  .i_rdy(w_data_req),.o_data(w_data),.o_valid(w_data_rdy));
  
  SPI_Master16bit SPI_GEN(.i_Rst_L(i_res_L),.i_Clk(i_clk),
                  .i_TX_Byte(w_data),.i_TX_DV(w_data_rdy),.o_TX_Ready(w_data_req),
                  .o_SPI_Clk(o_SPI_Clk),.o_SPI_MOSI(o_SPI_Data));
				
		
		
  // Purpose: Add clock delay to signals for alignment.
  always @(posedge i_clk or negedge i_res_L)
  begin
    if (~i_res_L)
    begin
      o_CS_L  <= 1'b0;
    end
    else
       o_CS_L <= w_data_req;   
  end 
  
                  
endmodule