module StrangeRAM (clk, addr, rdata, wdata, read, write, reset_n);

parameter ADDRSIZE = 1;
parameter WORDSIZE = 32;

input clk;
input [ADDRSIZE-1:0] addr;
output [WORDSIZE-1:0] rdata;
input [WORDSIZE-1:0] wdata;
input read,write;
input reset_n;

reg [WORDSIZE-1:0] Mem [0:(1<<ADDRSIZE)-1];

assign rdata = (read) ? (Mem[addr]+addr) : {WORDSIZE{1'bz}};

always @(posedge clk)
  if (write)
    Mem[addr] = wdata;

endmodule