version = 4.2

//
// Saved by sw version: 2023.2
//

model "flyback" {
    configuration {
        hil_device = "VHIL+"
        hil_configuration_id = 1
        simulation_method = exact
        simulation_time_step = .1e-6
        simulation_discret_scaling = 1.0
        dsp_timer_periods = 100e-6, 50e-3
        ss_calc_method = "systematic elimination"
        enb_pole_shift = True
        enb_gds_oversampling = True
        show_modes = False
        device_ao_limit_enable = False
        reset_analog_outputs_on_sim_stop = True
        reset_digital_outputs_on_sim_stop = True
        vhil_adio_loopback = False
        cpl_stb = False
        enb_dep_sw_detect = False
        code_section = "internal memory"
        data_section = "internal memory"
        sys_sp_rate_1 = 0.0001
        sys_sp_rate_2 = 0.05
        sys_real_type_precision = "default"
        user_real_type_precision = "default"
        sys_cpu_optimization = "high"
        user_cpu_optimization = "high"
        user_cpu_part_option = "default"
        matrix_based_reduction = True
        cpl_dynamics_analysis = False
        export_ss_to_pickle = False
        ground_scope_core = False
        dss_num_tol = 1e-15
        cce_platform = "generic"
        cce_use_relative_names = False
        cce_type_mapping_real = "double"
        cce_type_mapping_uint = "unsigned int"
        cce_type_mapping_int = "int"
        cce_directory = ""
        cce_custom_type_int = ""
        cce_custom_type_uint = ""
        cce_custom_type_real = ""
        tunable_params = "component defined"
        sp_compiler_type = "C compiler"
        sig_stim = "off"
        export_resource_list = ""
        export_dependency_list = ""
        excluded_resource_list = ""
        export_out_file = ""
        export_lock_top_level = True
        export_encrypt_library = True
        export_encrypt_resources = True
    }

    component Subsystem Root {
        component "core/Flyback" Flyback1 {
            L1 = "2.5e-6"
            L2 = "1e-7"
            Lm = "5e-4"
            R1 = "0.025"
            R2 = "0.001"
            ctrl_src = "Model"
            n1 = "20"
            n2 = "4"
            signal_access = "Inherit"
        }
        [
            position = 8224, 8408
            size = 144, 256
        ]

        component "core/Capacitor" Co {
            capacitance = "1.3e-3"
            initial_voltage = "5"
        }
        [
            position = 8400, 8360
            rotation = right
        ]

        component "core/Variable Resistor" Rl {
            inductance = "1e-6"
        }
        [
            position = 8752, 8360
            rotation = right
            size = 64, 48
        ]

        component "core/SCADA Input" Rl_eq {
            def_value = "0.5"
            execution_rate = "5e-7"
            max = "5"
            min = "0.5"
            unit = ""
        }
        [
            position = 8896, 8360
            scale = -1, 1
        ]

        component "core/Signal Controlled Voltage Source" Vi {
        }
        [
            position = 7840, 8408
            rotation = right
            scale = -1, 1
            size = 64, 32
        ]

        component "core/SCADA Input" Vin {
            def_value = "48"
            execution_rate = "5e-7"
            max = "72"
            min = "32"
            unit = ""
        }
        [
            position = 7688, 8408
        ]

        component "core/Voltage Measurement" Vo {
            execution_rate = "5e-7"
            sig_output = "True"
            signal_access = "Inherit"
            signal_name = "Vo"
        }
        [
            position = 8592, 8360
            rotation = right
            size = 64, 32
        ]

        component "core/Current Measurement" Ii {
            execution_rate = "5e-7"
            sig_output = "True"
            signal_access = "Inherit"
            signal_name = "Ii"
        }
        [
            position = 7976, 8312
            size = 64, 32
        ]

        component "core/Sum" Sum1 {
            signs = "+-"
        }
        [
            position = 7792, 8072
        ]

        component "core/PID controller" "PID controller1" {
            controller_type = "PI"
            enb_anti_windup_out = "True"
            enb_output_limit_out = "True"
            ki = "892"
            kp = "2.92"
            lower_sat_lim = "0"
            upper_sat_lim = "6"
        }
        [
            position = 7904, 8072
        ]

        component "core/Comparator" Comparator1 {
        }
        [
            position = 8032, 8080
            scale = 1, -1
        ]

        component "core/SR Flip Flop" "SR Flip Flop1" {
        }
        [
            position = 8472, 8064
        ]

        component "core/Square Wave Source" "Square Wave Source1" {
            duty_cycle = "0.1"
            execution_rate = "5e-7"
            frequency = "70000"
        }
        [
            position = 8192, 7928
        ]

        component "core/Logical operator" "Logical operator1" {
        }
        [
            position = 8320, 7984
        ]

        component "core/Logical operator" "Logical operator2" {
            operator = "NOT"
        }
        [
            position = 8192, 7992
        ]

        component "core/Constant" Constant1 {
            execution_rate = "5e-7"
            value = "5"
        }
        [
            position = 7672, 8064
        ]

        component "core/Termination" Termination1 {
        }
        [
            position = 8656, 8080
        ]

        component "core/Probe" PI {
        }
        [
            position = 8016, 7992
        ]

        component "core/Probe" Reset {
        }
        [
            position = 8184, 8144
        ]

        component "core/Probe" Set {
        }
        [
            position = 8464, 7984
        ]

        component "core/Probe" Q {
        }
        [
            position = 8616, 8016
        ]

        junction Junction1 pe
        [
            position = 8400, 8312
        ]

        junction Junction2 pe
        [
            position = 8400, 8408
        ]

        junction Junction3 pe
        [
            position = 8592, 8312
        ]

        junction Junction4 pe
        [
            position = 8592, 8408
        ]

        junction Junction6 sp
        [
            position = 7968, 8072
        ]

        junction Junction7 sp
        [
            position = 8096, 8080
        ]

        junction Junction8 sp
        [
            position = 8096, 8080
        ]

        junction Junction9 sp
        [
            position = 8400, 7984
        ]

        junction Junction10 sp
        [
            position = 8552, 8048
        ]

        connect Co.p_node Junction1 as Connection13
        connect Junction1 Flyback1.a_out as Connection14
        [
            breakpoints = 8400, 8312
        ]
        connect Co.n_node Junction2 as Connection16
        connect Junction2 Flyback1.b_out as Connection17
        [
            breakpoints = 8400, 8408
        ]
        connect Vi.n_node Flyback1.b_in as Connection21
        connect Rl_eq.out Rl.In as Connection23
        connect Rl.p_node Junction3 as Connection24
        connect Junction3 Junction1 as Connection25
        connect Vo.p_node Junction3 as Connection26
        connect Rl.n_node Junction4 as Connection27
        connect Junction4 Junction2 as Connection28
        connect Vo.n_node Junction4 as Connection29
        connect Vin.out Vi.in as Connection30
        connect Vi.p_node Ii.p_node as Connection31
        connect Ii.n_node Flyback1.a_in as Connection32
        connect Vo.out Sum1.in1 as Connection33
        [
            breakpoints = 8624, 8192; 7752, 8192
        ]
        connect "PID controller1.in" Sum1.out as Connection35
        connect Comparator1.in1 Ii.out as Connection37
        connect "Logical operator2.out" "Logical operator1.in1" as Connection42
        connect "Square Wave Source1.out" "Logical operator1.in" as Connection43
        connect Sum1.in Constant1.out as Connection46
        connect Termination1.in "SR Flip Flop1.out_n" as Connection52
        connect "PID controller1.out" Junction6 as Connection53
        connect Junction6 Comparator1.in2 as Connection54
        [
            breakpoints = 7968, 8072
        ]
        connect PI.in Junction6 as Connection55
        connect "SR Flip Flop1.r_in" Junction7 as Connection61
        [
            breakpoints = 8112, 8080
        ]
        connect Junction7 Comparator1.out as Connection62
        connect "Logical operator2.in" Junction8 as Connection64
        [
            breakpoints = 8096, 7992
        ]
        connect Junction8 Junction7 as Connection65
        [
            breakpoints = 8096, 8080
        ]
        connect Reset.in Junction8 as Connection66
        connect "Logical operator1.out" Junction9 as Connection67
        connect Junction9 "SR Flip Flop1.s_in" as Connection68
        [
            breakpoints = 8400, 7984; 8400, 8048
        ]
        connect Set.in Junction9 as Connection69
        connect "SR Flip Flop1.out" Junction10 as Connection70
        connect Junction10 Flyback1.s_ctrl as Connection71
        [
            breakpoints = 8552, 8048; 8552, 8240; 8224, 8240
        ]
        connect Q.in Junction10 as Connection72
    }

    default {
        "core/Capacitor" {
            capacitance = "1e-6"
            initial_voltage = "0"
            pole_shift_ignore = "False"
            visible = "True"
        }

        "core/Comparator" {
            execution_rate = "inherit"
        }

        "core/Constant" {
            value = "1"
            signal_type = "real"
            execution_rate = "100e-6"
            _tunable = "False"
        }

        "core/Logical operator" {
            operator = "AND"
            inputs = "2"
            execution_rate = "inherit"
        }

        "core/PID controller" {
            controller_type = "PID"
            kp = "1"
            kp_source = "internal"
            ki = "1"
            ki_source = "internal"
            kd = "0"
            kd_source = "internal"
            filt_coef = "100"
            int_init_value = "0"
            filt_init_value = "0"
            enb_output_limit_out = "False"
            show_reset = "none"
            upper_sat_lim = "1"
            upper_sat_lim_source = "internal"
            lower_sat_lim = "-1"
            lower_sat_lim_source = "internal"
            enb_anti_windup_out = "False"
            signal_out_type = "inherit"
            _tunable = "False"
            execution_rate = "inherit"
        }

        "core/Probe" {
            signal_access = "inherit"
            addr = "0"
            override_signal_name = "False"
            signal_name = ""
            signal_type = "generic"
            streaming_en = "False"
            streaming_er_idx = "0"
            execution_rate = "inherit"
        }

        "core/SCADA Input" {
            addr = "0"
            format = "real"
            override_signal_name = "False"
            signal_name = ""
            signal_type = "real"
            min = "-1e6"
            max = "1e6"
            def_value = "0"
            unit = " "
            execution_rate = "100e-6"
        }

        "core/SR Flip Flop" {
            init_value = "0"
            execution_rate = "inherit"
        }

        "core/Square Wave Source" {
            hs_output = "1"
            ls_output = "0"
            frequency = "50"
            duty_cycle = "0.5"
            phase = "0"
            signal_type = "real"
            execution_rate = "100e-6"
            _tunable = "False"
        }

        "core/Sum" {
            signs = "2"
            execution_rate = "inherit"
        }

        "core/Termination" {
            execution_rate = "inherit"
        }

        "core/Current Measurement" {
            signal_access = "inherit"
            bw_limit = "False"
            frequency = "10e3"
            comparator_enable = "False"
            operator = "greater"
            threshold = "0"
            cmp_abs_value = "False"
            feed_forward = "false"
            sig_output = "False"
            sig_output_filt_and_full_bw = "False"
            execution_rate = "100e-6"
            addr = "0"
            nd_msr_estimation = "false"
            dev_cpl_msr = "false"
            host_device = "0"
            output_to_device = "0"
            dev_cpl_index = "0"
            dev_cpl_var_nb = "0"
            visible = "True"
            override_signal_name = "False"
            signal_name = ""
        }

        "core/Flyback" {
            signal_access = "inherit"
            ctrl_src = "Digital inputs"
            op_mode = "Fixed carrier frequency"
            carrier_freq = "10000.0"
            carr_ph_offset = "0.0"
            d_time = "5e-6"
            ref_sig_min_max = "[-1.0, 1.0]"
            load_mode = "on min"
            execution_rate = "inherit"
            S1 = "1"
            S1_logic = "active high"
            show_monitoring = "False"
            n1 = "1"
            n2 = "1"
            L1 = "0.001"
            I1 = "0"
            L2 = "0.001"
            I2 = "0"
            Lm = "5"
            R1 = "0.1"
            R2 = "0.1"
            Rm = "1e4"
            pwm_enabling = "False"
            pwm_enable_di = "13"
            pwm_enable_inv = "active high"
        }

        "core/Signal Controlled Voltage Source" {
            execution_rate = "inherit"
        }

        "core/Variable Resistor" {
            inductance = "1e-3"
            initial_current = "0.0"
            hide_int_meas = "False"
        }

        "core/Voltage Measurement" {
            signal_access = "inherit"
            bw_limit = "False"
            frequency = "10e3"
            comparator_enable = "False"
            operator = "greater"
            threshold = "0"
            cmp_abs_value = "False"
            feed_forward = "false"
            sig_output = "False"
            sig_output_filt_and_full_bw = "False"
            execution_rate = "100e-6"
            addr = "0"
            nd_msr_estimation = "false"
            dev_cpl_msr = "false"
            host_device = "0"
            output_to_device = "0"
            dev_cpl_index = "0"
            dev_cpl_var_nb = "0"
            visible = "True"
            override_signal_name = "False"
            signal_name = ""
        }
    }
}