// -------------------------------------------------------------
//
// Module: HlpB1
//
// Generated by MATLAB(R) 7.8 and the Filter Design HDL Coder 2.4.
//
// Generated on: 2010-08-09 16:40:08
//
// -------------------------------------------------------------

// -------------------------------------------------------------
// HDL Code Generation Options:
//
// TargetDirectory: C:\Users\marsi\Documents\Altera\my_projects\tutorial6
// Name: HlpB1
// CoefficientSource: ProcessorInterface
// ResetAssertedLevel: Active-low
// TargetLanguage: Verilog
// TestBenchName: Hlp_tb
//
// Filter Settings:
//
// Discrete-Time IIR Filter (real)
// -------------------------------
// Filter Structure    : Direct-Form II, Second-Order Sections
// Number of Sections  : 1
// Stable              : Yes
// Linear Phase        : No
// Arithmetic          : fixed
// Numerator           : s8,7 -> [-1 1)
// Denominator         : s8,6 -> [-2 2)
// Scale Values        : s8,8 -> [-5.000000e-001 5.000000e-001)
// Input               : s32,0 -> [-2.147484e+009 2.147484e+009)
// Section Input       : s32,-3 -> [-1.717987e+010 1.717987e+010)
// Section Output      : s32,-3 -> [-1.717987e+010 1.717987e+010)
// Output              : s32,-3 -> [-1.717987e+010 1.717987e+010)
// State               : s32,0 -> [-2.147484e+009 2.147484e+009)
// Numerator Prod      : s40,7 -> [-4.294967e+009 4.294967e+009)
// Denominator Prod    : s40,6 -> [-8.589935e+009 8.589935e+009)
// Numerator Accum     : s40,5 -> [-1.717987e+010 1.717987e+010)
// Denominator Accum   : s40,4 -> [-3.435974e+010 3.435974e+010)
// Round Mode          : convergent
// Overflow Mode       : saturate
// Cast Before Sum     : true
// -------------------------------------------------------------
`timescale 1 ns / 1 ns

module HlpB6
               (
	             clk,
					 reset,
                valid_in,
                filter_in,
					 ready_out,
                write,
                address,
                coeffs_in,
                filter_out,
					 valid_out,
					 ready_in
                );

  input   clk; 
  input   valid_in; 
  input   reset; 
  input   signed [31:0] filter_in; //sfix32
  input   write; 
  input   [3:0] address; //ufix3
  input   signed [7:0] coeffs_in; //sfix8
  output  signed [31:0] filter_out; //sfix32_E3
  output  reg valid_out;
  output  wire ready_out;
  input   wire ready_in;

////////////////////////////////////////////////////////////////
//Module Architecture: HlpB1
////////////////////////////////////////////////////////////////
  // Local Functions
  // Type Definitions
  // Constants
  // Signals
  reg  signed [31:0] input_register; // sfix32
  reg  write_reg; // boolean
  wire  done_assigned; // boolean
  reg  [3:0] address_reg; // ufix3
  reg  signed [7:0] coeffs_in_reg; // sfix8
  // Section 1   Processor Interface Signals 
  wire signed [7:0] coeff_scale1_assigned; // sfix8_En8
  wire signed [7:0] coeff_scale1_temp; // sfix8_En8
  reg  signed [7:0] coeff_scale1_reg; // sfix8_En8
  reg  signed [7:0] coeff_scale1_shadow_reg; // sfix8_En8
  wire signed [31:0] scale1; // sfix32_E3
  wire signed [39:0] mul_temp; // sfix40_En8
  wire signed [7:0] coeff_b1_section1_assigned; // sfix8_En7
  wire signed [7:0] coeff_b1_section1_temp; // sfix8_En7
  reg  signed [7:0] coeff_b1_section1_reg; // sfix8_En7
  reg  signed [7:0] coeff_b1_section1_shadow_reg; // sfix8_En7
  wire signed [7:0] coeff_b2_section1_assigned; // sfix8_En7
  wire signed [7:0] coeff_b2_section1_temp; // sfix8_En7
  reg  signed [7:0] coeff_b2_section1_reg; // sfix8_En7
  reg  signed [7:0] coeff_b2_section1_shadow_reg; // sfix8_En7
  wire signed [7:0] coeff_b3_section1_assigned; // sfix8_En7
  wire signed [7:0] coeff_b3_section1_temp; // sfix8_En7
  reg  signed [7:0] coeff_b3_section1_reg; // sfix8_En7
  reg  signed [7:0] coeff_b3_section1_shadow_reg; // sfix8_En7
  wire signed [7:0] coeff_a2_section1_assigned; // sfix8_En6
  wire signed [7:0] coeff_a2_section1_temp; // sfix8_En6
  reg  signed [7:0] coeff_a2_section1_reg; // sfix8_En6
  reg  signed [7:0] coeff_a2_section1_shadow_reg; // sfix8_En6
  wire signed [7:0] coeff_a3_section1_assigned; // sfix8_En6
  wire signed [7:0] coeff_a3_section1_temp; // sfix8_En6
  reg  signed [7:0] coeff_a3_section1_reg; // sfix8_En6
  reg  signed [7:0] coeff_a3_section1_shadow_reg; // sfix8_En6
  wire  [7:0] coeff_shift_assigned; // sfix8_En6
  wire  [7:0] coeff_shift_temp; // sfix8_En6
  reg   [7:0] coeff_shift_reg; // sfix8_En6
  reg   [7:0] coeff_shift_shadow_reg; // sfix8_En6
  // Section 1 Signals 
  wire signed [39:0] a1sum1; // sfix40_En4
  wire signed [39:0] a2sum1; // sfix40_En4
  wire signed [39:0] b1sum1; // sfix40_En5
  wire signed [39:0] b2sum1; // sfix40_En5
  wire signed [31:0] typeconvert1; // sfix32
  reg  signed [31:0] delay_section1 [0:1] ; // sfix32
  wire signed [31:0] inputconv1; // sfix32_E3
  wire signed [39:0] a2mul1; // sfix40_En6
  wire signed [39:0] a3mul1; // sfix40_En6
  wire signed [39:0] b1mul1; // sfix40_En7
  wire signed [39:0] b2mul1; // sfix40_En7
  wire signed [39:0] b3mul1; // sfix40_En7
  wire signed [39:0] sub_cast; // sfix40_En4
  wire signed [39:0] sub_cast_1; // sfix40_En4
  wire signed [40:0] sub_temp; // sfix41_En4
  wire signed [39:0] sub_cast_2; // sfix40_En4
  wire signed [39:0] sub_cast_3; // sfix40_En4
  wire signed [40:0] sub_temp_1; // sfix41_En4
  wire signed [39:0] b1multypeconvert1; // sfix40_En5
  wire signed [39:0] add_cast; // sfix40_En5
  wire signed [39:0] add_cast_1; // sfix40_En5
  wire signed [40:0] add_temp; // sfix41_En5
  wire signed [39:0] add_cast_2; // sfix40_En5
  wire signed [39:0] add_cast_3; // sfix40_En5
  wire signed [40:0] add_temp_1; // sfix41_En5
  wire signed [31:0] section_result1; // sfix32_E3
  // Last Section Value --   Processor Interface Signals 
  wire signed [7:0] coeff_scale2_assigned; // sfix8_En8
  wire signed [7:0] coeff_scale2_temp; // sfix8_En8
  reg  signed [7:0] coeff_scale2_reg; // sfix8_En8
  reg  signed [7:0] coeff_scale2_shadow_reg; // sfix8_En8
  wire signed [31:0] scale2; // sfix32_E3
  wire signed [39:0] mul_temp_1; // sfix40_En5
  wire signed [31:0] output_typeconvert; // sfix32_E3
  reg  signed [31:0] output_register; // sfix32_E3

  // Block Statements
  always @ (posedge clk or negedge reset)
    begin: input_reg_process
      if (reset == 1'b0) begin
        write_reg <= 1'b0;
        address_reg <= 0;
        coeffs_in_reg <= 0;
		  valid_out <= 0;
      end
      else begin
          write_reg <= write;
          address_reg <= address;
          coeffs_in_reg <= coeffs_in;
			 valid_out <= valid_in;
      end
    end // input_reg_process
	 
	 always @ (posedge clk or negedge reset)
    begin: input_sample_process
      if (reset == 1'b0) 
        input_register <= 0;
      else 
        if (valid_in == 1'b1) 
          input_register <= filter_in;
    end // input_sample_process
	 
	 

  //   -------- Section 1 Processor Interface logic------------------

  assign mul_temp = input_register * coeff_scale1_shadow_reg;
  assign scale1 = ({{3{mul_temp[39]}}, mul_temp[39:0]} + {mul_temp[11], {10{~mul_temp[11]}}})>>>11;

  assign coeff_scale1_assigned = (address_reg == 4'b0000) ? coeffs_in_reg :
                           coeff_scale1_reg;
  assign coeff_scale1_temp = (write_reg == 1'b1) ? coeff_scale1_assigned :
                       coeff_scale1_reg;
  assign coeff_b1_section1_assigned = (address_reg == 4'b0001) ? coeffs_in_reg :
                                coeff_b1_section1_reg;
  assign coeff_b1_section1_temp = (write_reg == 1'b1) ? coeff_b1_section1_assigned :
                            coeff_b1_section1_reg;
  assign coeff_b2_section1_assigned = (address_reg == 4'b0010) ? coeffs_in_reg :
                                coeff_b2_section1_reg;
  assign coeff_b2_section1_temp = (write_reg == 1'b1) ? coeff_b2_section1_assigned :
                            coeff_b2_section1_reg;
  assign coeff_b3_section1_assigned = (address_reg == 4'b0011) ? coeffs_in_reg :
                                coeff_b3_section1_reg;
  assign coeff_b3_section1_temp = (write_reg == 1'b1) ? coeff_b3_section1_assigned :
                            coeff_b3_section1_reg;
  assign coeff_a2_section1_assigned = (address_reg == 4'b0100) ? coeffs_in_reg :
                                coeff_a2_section1_reg;
  assign coeff_a2_section1_temp = (write_reg == 1'b1) ? coeff_a2_section1_assigned :
                            coeff_a2_section1_reg;
  assign coeff_a3_section1_assigned = (address_reg == 4'b0101) ? coeffs_in_reg :
                                coeff_a3_section1_reg;
  assign coeff_a3_section1_temp = (write_reg == 1'b1) ? coeff_a3_section1_assigned :
                            coeff_a3_section1_reg;
  assign coeff_shift_assigned = (address_reg == 4'b0110) ? coeffs_in_reg :
                                coeff_shift_reg;
  assign coeff_shift_temp = (write_reg == 1'b1) ? coeff_shift_assigned :
                            coeff_shift_reg;
  assign done_assigned = (address_reg == 4'b1000) ? write_reg	: 1'b0;					 
									 
  always @ (posedge clk or negedge reset)
    begin: coeff_reg_process_section1
      if (reset == 1'b0) begin
        coeff_scale1_reg <= 0;
        coeff_b1_section1_reg <= 0;
        coeff_b2_section1_reg <= 0;
        coeff_b3_section1_reg <= 0;
        coeff_a2_section1_reg <= 0;
        coeff_a3_section1_reg <= 0;
        coeff_shift_reg <= 0;
		  end
      else begin
          coeff_scale1_reg <= coeff_scale1_temp;
          coeff_b1_section1_reg <= coeff_b1_section1_temp;
          coeff_b2_section1_reg <= coeff_b2_section1_temp;
          coeff_b3_section1_reg <= coeff_b3_section1_temp;
          coeff_a2_section1_reg <= coeff_a2_section1_temp;
          coeff_a3_section1_reg <= coeff_a3_section1_temp;
          coeff_shift_reg <= coeff_shift_temp;
      end
    end // coeff_reg_process_section1

  always @ (posedge clk or negedge reset)
    begin: coeff_shadow_reg_process_section1
      if (reset == 1'b0) begin
        coeff_scale1_shadow_reg <= 0;
        coeff_b1_section1_shadow_reg <= 0;
        coeff_b2_section1_shadow_reg <= 0;
        coeff_b3_section1_shadow_reg <= 0;
        coeff_a2_section1_shadow_reg <= 0;
        coeff_a3_section1_shadow_reg <= 0;
        coeff_shift_shadow_reg <= 0;
      end
      else begin
        if (done_assigned == 1'b1) begin
          coeff_scale1_shadow_reg <= coeff_scale1_reg;
          coeff_b1_section1_shadow_reg <= coeff_b1_section1_reg;
          coeff_b2_section1_shadow_reg <= coeff_b2_section1_reg;
          coeff_b3_section1_shadow_reg <= coeff_b3_section1_reg;
          coeff_a2_section1_shadow_reg <= coeff_a2_section1_reg;
          coeff_a3_section1_shadow_reg <= coeff_a3_section1_reg;
          coeff_shift_shadow_reg <= coeff_shift_reg;
			 end
      end
    end // coeff_shadow_reg_process_section1

  //   ------------------ Section 1 ------------------

  assign typeconvert1 = ((a1sum1[39] == 1'b0 & a1sum1[38:35] != 4'b0000) || (a1sum1[39] == 1'b0 && a1sum1[35:4] == 32'b01111111111111111111111111111111) // special case0
) ? 32'b01111111111111111111111111111111 : 
      (a1sum1[39] == 1'b1 && a1sum1[38:35] != 4'b1111) ? 32'b10000000000000000000000000000000 : ({a1sum1[39], a1sum1[35:0] + {a1sum1[4], {3{~a1sum1[4]}}}})>>>4;

  always @( posedge clk or negedge reset)
    begin: delay_process_section1
      if (reset == 1'b0) begin
        delay_section1[0] <= 0;
        delay_section1[1] <= 0;
      end
      else begin
        if (valid_in == 1'b1) begin
          delay_section1[0] <= typeconvert1;
          delay_section1[1] <= delay_section1[0];
        end
      end
    end // delay_process_section1


  assign inputconv1 = scale1;

  assign a2mul1 = delay_section1[0] * coeff_a2_section1_shadow_reg;

  assign a3mul1 = delay_section1[1] * coeff_a3_section1_shadow_reg;

  assign b1mul1 = typeconvert1 * coeff_b1_section1_shadow_reg;

  assign b2mul1 = delay_section1[0] * coeff_b2_section1_shadow_reg;

  assign b3mul1 = delay_section1[1] * coeff_b3_section1_shadow_reg;

  assign sub_cast = $signed({inputconv1, 7'b0000000});
  assign sub_cast_1 = ({{2{a2mul1[39]}}, a2mul1[39:0]} + {a2mul1[2], {1{~a2mul1[2]}}})>>>2;
  assign sub_temp = sub_cast - sub_cast_1;
  assign a2sum1 = ((sub_temp[40] == 1'b0 & sub_temp[39] != 1'b0) || (sub_temp[40] == 1'b0 && sub_temp[39:0] == 40'b0111111111111111111111111111111111111111) // special case0
) ? 40'b0111111111111111111111111111111111111111 : 
      (sub_temp[40] == 1'b1 && sub_temp[39] != 1'b1) ? 40'b1000000000000000000000000000000000000000 : sub_temp[39:0];

  assign sub_cast_2 = a2sum1;
  assign sub_cast_3 = ({{2{a3mul1[39]}}, a3mul1[39:0]} + {a3mul1[2], {1{~a3mul1[2]}}})>>>2;
  assign sub_temp_1 = sub_cast_2 - sub_cast_3;
  assign a1sum1 = ((sub_temp_1[40] == 1'b0 & sub_temp_1[39] != 1'b0) || (sub_temp_1[40] == 1'b0 && sub_temp_1[39:0] == 40'b0111111111111111111111111111111111111111) // special case0
) ? 40'b0111111111111111111111111111111111111111 : 
      (sub_temp_1[40] == 1'b1 && sub_temp_1[39] != 1'b1) ? 40'b1000000000000000000000000000000000000000 : sub_temp_1[39:0];

  assign b1multypeconvert1 = ({{2{b1mul1[39]}}, b1mul1[39:0]} + {b1mul1[2], {1{~b1mul1[2]}}})>>>2;

  assign add_cast = b1multypeconvert1;
  assign add_cast_1 = ({{2{b2mul1[39]}}, b2mul1[39:0]} + {b2mul1[2], {1{~b2mul1[2]}}})>>>2;
  assign add_temp = add_cast + add_cast_1;
  assign b2sum1 = ((add_temp[40] == 1'b0 & add_temp[39] != 1'b0) || (add_temp[40] == 1'b0 && add_temp[39:0] == 40'b0111111111111111111111111111111111111111) // special case0
) ? 40'b0111111111111111111111111111111111111111 : 
      (add_temp[40] == 1'b1 && add_temp[39] != 1'b1) ? 40'b1000000000000000000000000000000000000000 : add_temp[39:0];

  assign add_cast_2 = b2sum1;
  assign add_cast_3 = ({{2{b3mul1[39]}}, b3mul1[39:0]} + {b3mul1[2], {1{~b3mul1[2]}}})>>>2;
  assign add_temp_1 = add_cast_2 + add_cast_3;
  assign b1sum1 = ((add_temp_1[40] == 1'b0 & add_temp_1[39] != 1'b0) || (add_temp_1[40] == 1'b0 && add_temp_1[39:0] == 40'b0111111111111111111111111111111111111111) // special case0
) ? 40'b0111111111111111111111111111111111111111 : 
      (add_temp_1[40] == 1'b1 && add_temp_1[39] != 1'b1) ? 40'b1000000000000000000000000000000000000000 : add_temp_1[39:0];

  assign section_result1 = (b1sum1[39] == 1'b0 && b1sum1[38:7] == 32'b11111111111111111111111111111111) ? 32'b01111111111111111111111111111111 : ({b1sum1[39], b1sum1[39:0] + {b1sum1[8], {7{~b1sum1[8]}}}})>>>8;

  //   -------- Last Section Value -- Processor Interface logic------------------

  assign mul_temp_1 = section_result1 * coeff_scale2_shadow_reg;
  assign scale2 = (mul_temp_1[39] == 1'b0 && mul_temp_1[38:7] == 32'b11111111111111111111111111111111) ? 32'b01111111111111111111111111111111 : ({mul_temp_1[39], mul_temp_1[39:0] + {mul_temp_1[8], {7{~mul_temp_1[8]}}}})>>>8;

  assign coeff_scale2_assigned = (address_reg == 4'b0111) ? coeffs_in_reg :
                           coeff_scale2_reg;
  assign coeff_scale2_temp = (write_reg == 1'b1) ? coeff_scale2_assigned :
                       coeff_scale2_reg;
  
  always @ (posedge clk or negedge reset)
    begin: coeff_reg_process_Last_ScaleValue
      if (reset == 1'b0) begin
        coeff_scale2_reg <= 0;
      end
      else begin
          coeff_scale2_reg <= coeff_scale2_temp;
      end
    end // coeff_reg_process_Last_ScaleValue

  always @ (posedge clk or negedge reset)
    begin: coeff_shadow_reg_process_Last_ScaleValue
      if (reset == 1'b0) 
        coeff_scale2_shadow_reg <= 0;
      else 
        if (done_assigned == 1'b1) 
          coeff_scale2_shadow_reg <= coeff_scale2_reg;
		
    end // coeff_shadow_reg_process_Last_ScaleValue

  assign output_typeconvert = scale2;

  always @ (posedge clk or negedge reset)
    begin: Output_Register_process
      if (reset == 1'b0) begin
        output_register <= 0;
      end
      else begin
        if (valid_in == 1'b1) begin
          output_register <= output_typeconvert;
        end
      end
    end // Output_Register_process

  // Assignment Statements
  assign filter_out = output_register <<< coeff_shift_shadow_reg;
  assign ready_out =ready_in;
  
endmodule  // HlpB6