// Quartus Prime Verilog Template
// Binary counter

module Modular_counter_sync
#(parameter MODULE=9)
(
	input clk, enable, reset,
	output reg [3:0] count,
	output carry
);

	// Reset if needed, or increment if counting is enabled
	always @ (posedge clk)
	begin
		if (reset)
			count <= 4'b0000;
	   else 
			begin
				if (enable == 1'b1)
					if (count == MODULE) 
						count <= 4'b0000;
					else 
						count <= count +4'b0001;
			end
	end
	
	// Carry Generate ....
	
endmodule