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//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//tempput files any of the foregoing (including device programming or
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module hex7(in, out, clock);

input		clock;
input 		[3:0] in;
output 		[6:0] out;
reg			[6:0]temp;

assign out=(clock)?temp:7'd0;

always @(in)
begin
		case(in)
		4'h1: temp = 7'b1111001;		// ---t----
		4'h2: temp = 7'b0100100; 	// |	  |
		4'h3: temp = 7'b0110000; 	// lt	 rt
		4'h4: temp = 7'b0011001; 	// |	  |
		4'h5: temp = 7'b0010010; 	// ---m----
		4'h6: temp = 7'b0000010; 	// |	  |
		4'h7: temp = 7'b1111000; 	// lb	 rb
		4'h8: temp = 7'b0000000; 	// |	  |
		4'h9: temp = 7'b0011000; 	// ---b----
		4'ha: temp = 7'b0001000;
		4'hb: temp = 7'b0000011;
		4'hc: temp = 7'b1000110;
		4'hd: temp = 7'b0100001;
		4'he: temp = 7'b0000110;
		4'hf: temp = 7'b0001110;
		4'h0: temp = 7'b1000000;
		endcase
end

endmodule



