/*
 * testbench_for_vgafb.v
 * 
 * Verilog Tetris testbench for VGA framebuffer subsystem - FPGA class project
 * 
 * 
 * Authors: Iva Pertot - Erik Petaros 
 * Contact: <ivapertot@gmail.com>
 * Release date: jan 2013
 * 
 * 
 * 
 * This program is free software; you can redistribute it and/or modify
 * 
 * it under the terms of the GNU General Public License as published by
 * 
 * the Free Software Foundation; either version 2 of the License, or
 * 
 * (at your option) any later version.
 * 
 * 
 * 
 * This program is distributed in the hope that it will be useful,
 * 
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * 
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * 
 * GNU General Public License for more details.
 * 
 * 
 * 
 * You should have received a copy of the GNU General Public License
 * 
 * along with this program; if not, write to the Free Software
 * 
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * 
 * MA 02110-1301, USA.
 * 
 */

module testbench(

	sram_address, sram_data, sram_writereq, sram_writeack,
	clock, reset,
	bufselect,
	
	);

	
input clock, reset;

output reg [15:0] sram_data;
output reg [17:0] sram_address;

output reg bufselect;

output reg sram_writereq;
input sram_writeack;

reg [2:0] status;
reg [9:0] Xcount;
reg [8:0] Ycount;


reg rtemp, btemp;
reg [1:0] gtemp;

// test pattern!
always @ (posedge clock or posedge reset)
begin
	if (reset) begin
		sram_address<=0;
		status<=0;
		Xcount<=0;
		Ycount<=0;
		bufselect<=0;
	end else begin
		
		case (status)
			2'd0:
				begin
					if ((sram_address != 18'd76799) && (sram_writeack==1'b0) ) begin
							status<=1;
							sram_address<=sram_address+1;
							sram_writereq<=1'b1;
							if (Xcount < 200) begin
								rtemp = 1;
								btemp=1;
							end else if (Xcount > 400) begin
								rtemp=1;
								btemp=0;
							end else begin
								rtemp = 0;
								btemp=1;
							end
							if (Ycount < 150)
								gtemp = 0;
							else if (Ycount >300)
								gtemp = 2;
							else
								gtemp = 3;
							//sram_data <= {sram_address[7:0],sram_address[7:0]}; 
							//sram_data <= {16'hAAAA}; 
							sram_data <= {btemp,gtemp,rtemp,btemp,gtemp,rtemp,btemp,gtemp,rtemp,btemp,gtemp,rtemp};
							
							if (Xcount != 636)
								Xcount<=Xcount+4;
							else begin
								Xcount <= 0;
								if (Ycount != 479) Ycount <= Ycount+1;
								// else Ycount <= 0;
							end

					
					end else begin
						sram_writereq<=1'b0;
					end
				end
			2'd1:
				begin
					
					
					if (sram_writeack) begin
						sram_writereq<=1'b0;
						status<=0;
					end
					
				end
		endcase
		
	end
	
end


endmodule
