-- EXAMPLE: VHDL CODE FOR OR GATE ———————————————————————————

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity or_gate is
Port (
	A : in STD_LOGIC;
	B : in STD_LOGIC;
	Y : out STD_LOGIC
);
end or_gate;

architecture or_arch of or_gate is

begin
Y <= A or B; 

end or_arch;

-- EXAMPLE: TEST BENCH FOR OR GATE ———————————————————————————
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity or_gate_tb is
end or_gate_tb;

architecture or_gate_tb_arch of or_gate_tb is

component or_gate
Port (
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC
);
end component;

signal A_tb : STD_LOGIC := '0';
signal B_tb : STD_LOGIC := '0';
signal Y_tb : STD_LOGIC;

begin

dut: or_gate
port map (
A => A_tb,
B => B_tb,
Y => Y_tb
);

stim_proc: process
begin

	-- Test 1
A_tb <= '0'; B_tb <= '0';
wait for 10 ns; 

assert (Y_tb = '0')
report "Error Test 1 00"
severity error;

	-- Test 2
A_tb <= '0'; B_tb <= '1';
wait for 10 ns;

assert (Y_tb = '1')
report "Error Test 2 01"
severity error;

	-- Test 3
A_tb <= '1'; B_tb <= '0';
wait for 10 ns;
assert (Y_tb = '1')
report "Error Test 3 10"
severity error;

	-- Test 4
A_tb <= '1'; B_tb <= '1';
wait for 10 ns;
assert (Y_tb = '1')
report "Error Test 4 11"
severity error;

report "Test completato con successo"
severity note;

wait; 
end process;

end or_gate_tb_arch;