Schema della sezione

    • Software Installation Note File TXT
    • HPS Patch for DDR3 File

      https://www.intel.com/content/www/us/en/support/programmable/articles/000088789.html

      Description
      Due to a problem in the Quartus® Prime Standard Edition Software version 21.1, you may not be able to Generate HDL for your Platform Designer system in the Windows operating system (OS). The problem may occur if your system includes the DDR3 SDRAM Controller with UniPHY IP core.

      Error: border: Error during execution of script generate_hps_sdram.tcl: seq: Error during execution of "{C:/intelfpga/21.1/quartus/../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally 
      Resolution
      To work around this problem, download and install the patch below according to the versions of your Quartus® Prime Standard Edition Software.

      This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software. 

    • FPGA Academy URL
    • DE1-Soc from Terasic URL
    • Modelsim v.16 URL
    • Altera Monitor Program URL