Topic outline
01 - Programmable logic devices and ASICs
02 - Fundamental concepts of VHDL
03 - Scalar data types and their operations
04 - Sequential statements
05 - Composite data types and their operations
06 - Basic system modeling concepts
Lab 0A
Lab 0B
14B - VHDL Synthesis
Lab 01
07 - Subprograms
Lab 02
08 - Packages and use clauses
09 - Resolved signals
Lab 03
10 - Predefined and Standard Packages
11 - Aliases
Lab 04
12 - Generic constants
13 - Components and configurations
14 - VHDL Synthesis
Lab 05
Lab 06
15 - High level design flow
16 - VHDL model of a processor
Lab 07
Lab 08
17 - Pipelined Mac
Lab 09
Lab 10