301MI - PROGETTAZIONE DI SISTEMI ELETTRONICI 2022: All participants

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01 - Programmable logic devices and ASICs

02 - Fundamental concepts of VHDL

03 - Scalar data types and their operations

04 - Sequential statements

05 - Composite data types and their operations

06 - Basic system modeling concepts

Lab 0A

Lab 0B

14B - VHDL Synthesis

07 - Subprograms

Lab 01

08 - Packages and use clauses

09 - Resolved signals

Lab 02

10 - Predefined and Standard Packages

Lab 03

Lab 04

11 - Aliases

12 - Generic constants

13 - Components and configurations

Lab 05

Lab 06

Lab 07

14 - VHDL Synthesis

15 - High level design flow

16 - VHDL model of a processor

Lab 08

Lab 09

Lab 10

17 - Pipelined Mac