Topic outline
- General
- 01 - Programmable logic devices and ASICs
01 - Programmable logic devices and ASICs
- 02 - Fundamental concepts of VHDL
02 - Fundamental concepts of VHDL
- 03 - Scalar data types and their operations
03 - Scalar data types and their operations
- 04 - Sequential statements
04 - Sequential statements
- 05 - Composite data types and their operations
05 - Composite data types and their operations
- 06 - Basic system modeling concepts
06 - Basic system modeling concepts
- Lab 0A
Lab 0A
- 07 - Subprograms
07 - Subprograms
- Lab 0B
Lab 0B
- 08 - Packages and use clauses
08 - Packages and use clauses
- Lab 01
Lab 01
- 09 - Resolved signals
09 - Resolved signals
- 10 - Predefined and Standard Packages
10 - Predefined and Standard Packages
- Lab 02
Lab 02
- 11 - Aliases
11 - Aliases
- 12 - Generic constants
12 - Generic constants
- 13 - Components and configurations
13 - Components and configurations
- 14 - VHDL Synthesis
14 - VHDL Synthesis
- Lab 03
Lab 03
- Lab 04
Lab 04
- 15 - High level design flow
15 - High level design flow
- Lab 05
Lab 05
- Lab 06
Lab 06
- 16 - VHDL model of a processor
16 - VHDL model of a processor
- Lab 07
Lab 07
- Lab 08
Lab 08
- 17 - Pipelined Mac
17 - Pipelined Mac
- Lab 11
Lab 11
- Lab 12
Lab 12